In recent years, a mobile telephone has been attracted as an information terminal for the Internet, wherein the mobile telephone is required to have a function of storing various kinds of data such as distributed image data and character data. The information terminal of such kind has an integration of a DRAM (Dynamic Random Access Memory) with a large capacity as a buffer memory for storing distributed data.
It is necessary for DRAM to perform cyclic operations for refreshing data stored in memory cells. A consumed current caused by this refresh operation depends on a storage capacity. In the refresh operation, data are re-written with sequential selections of rows of a memory cell array. If the storage capacity is large, then a large number of rows have to be selected in a unit time. For this reason, it is necessary to set a short cycle for refresh operation. Thus, a semiconductor memory with a large capacity shows a tendency to increase a power consumption caused by the refresh operation, resulting in an increased burden to a battery of the mobile telephone integrating this semiconductor memory.
If data with a small size have to be stored in a buffer memory of the mobile telephone, then the memory cell array of the DRAM has an increased ratio or proportion of an area free of any effective data, thereby causing unnecessary refresh operations with unnecessary consumption of current. A partial refresh mode has been know as an operation mode which suppresses generation of such unnecessary current consumption. Utilization of this partial refresh mode enables a selective refresh to a partial area which stores useful data, and effectively suppresses generation of an unnecessary current consumption.
In the field of mobile telephones, there is a requirement for adaptively switching operation modes such as refresh mode for DRAM over applications, dependent upon a scale of the stored data.
For the conventional DRAM, an input signal, which is uniquely specified in input timings, is necessary for switching the operation modes. This makes a timing design complicated in the side of a device integrated with DRAM of such kind.
The present invention was made in view of the above circumstances, and its object is to provide a semiconductor memory device and a method of entry of its operation modes for enabling entry of the operation modes during operations with effective suppression to any erroneous entry and without need of any special timing specification.